Currently used process flows for forming double polysilicon NPN transistors typically deposit the first polysilicon layer directly on an active silicon region in order to obtain electrical contact between the two layers. The polysilicon layer is then patterned to form the base contacts (electrodes) for the device. The patterning step can cause problems because the polysilicon layer must be etched (typically in a plasma etch) without etching too much of the underlying silicon layer. Since plasma etches are almost equally selective to both polysilicon and the active silicon (i.e., polysilicon and single crystal silicon are etched at nearly the same rate), any amount of over-etching of the polysilicon will remove the single crystal silicon beneath the polysilicon layer. This recesses the active silicon region of the device and alters the characteristics of the final transistor. For example, critical transistor parameters such as .beta. (the transistor gain), BV.sub.ebo (the emitter-base breakdown voltage), BV.sub.ceo (the collector-emitter breakdown voltage), and the base resistance can be affected by the polysilicon over-etch. Thus, in the case of a self-aligned double poly NPN process, over-etching of the polysilicon layer has undesirable consequences for the NPN device.
However, it is desirable in most double poly NPN process flows to significantly over-etch the polysilicon layer to prevent inadvertent shorting of the device due to formation of polysilicon "stringers". But, as noted, performing such an over-etch in a self-aligned polysilicon process will lead to etching of the underlying single crystal silicon. Thus, in such processes, a polysilicon over-etch is generally not performed, and, as a result, the process has a low yield.
Another disadvantage of conventional double polysilicon process flows is a lack of control of the characteristics of the emitter-extrinsic base junction. The location and dimensions of a recess used to form the junction, which is produced during the polysilicon (over)etch, is difficult to control and is a variable and often significant source of base resistance. This is because the base resistance is a strong function of the recess dimensions. Thus, the use of a polysilicon over-etch in a self-aligned double poly process flow has significant disadvantages that can overcome the advantage of reducing polysilicon stringers. These competing factors are subjected to a trade-off in most processes, with the result that sub-optimal transistors are produced with a medium to poor yield.
FIGS. 1(A) through 1(F) are side views showing the process flow for a conventional self-aligned double poly NPN transistor. As shown in FIG. 1(A), the process begins with a single crystal silicon substrate 102 in which is formed an N+ type buried layer 104 by implantation and diffusion of appropriate dopants. Next, an N- type epitaxial silicon layer 106 is grown over the surface of substrate 102. Isolation regions 108 (labelled "field oxide" in the figure) are then formed to define the epitaxial silicon active device region. A first polysilicon layer which will be used to form the base contact (electrode) for the device is then deposited over the surface of substrate 102. The polysilicon layer is doped to a P+ type by standard masking and implant steps. The device structure is then annealed to drive in the P+ type dopant, a producing P+ doped polysilicon layer 110. A layer of interpoly oxide 112 (or nitride) is then deposited over the surface of P+ type polysilicon layer 110.
Next, standard masking steps known in the semiconductor industry are used to pattern polysilicon layer 110 to define a location for the base contact. During the patterning step(s), an interpoly oxide layer 112 (or a nitride layer if one is used) is etched to remove appropriate portions of interpoly oxide layer 112 from the base contact location. This is followed by an etch of doped polysilicon layer 110 to remove appropriate portions of that layer. A link base implantation may then be performed (if desired) to reduce the base resistance of the final device. Note that if a polysilicon over-etch is performed to eliminate poly stringers, a recess 120 is formed in epitaxial silicon layer 106. The resulting structure is shown in FIG. 1(B).
Next, an oxide layer 122 is deposited over the surface of substrate 102. Oxide layer 122 will be used to form sidewall spacers for electrically isolating the transistor emitter from the source and drain regions. As shown in FIG. 1(C), oxide layer 122 fills in recess 120 formed in epitaxial silicon layer 106.
Sidewall spacers 123 are then formed using an etchback step which is more selective to oxide layer 122 than to interpoly oxide layer 112. The resulting structure is shown in FIG. 1(D).
An appropriate dopant is then implanted into the base region to form the intrinsic base (shown as P- base 124 in the figure). A second layer of polysilicon 126 is then deposited over the surface of substrate 102. Polysilicon layer 126 is then implanted with an appropriate N+ type dopant (e.g., Arsenic or Phosphorus) as part of the process of forming the emitter for the device. The resulting structure is shown in FIG. 1(E).
Next, a final anneal step is performed to drive in the implanted dopants and form the junctions for the device. As shown in FIG. 1(F), the anneal step causes the P+ type dopant in polysilicon layer 110 to be driven into epitaxial silicon layer 106 in the areas surrounding the P- type intrinsic base region 124. The anneal step also causes the N+ type dopant implanted into polysilicon layer 126 to be driven into epitaxial layer 106. As discussed, although the appropriate structure for the device can be constructed using these steps, the over-etch of polysilicon layer 110 causes etching into the epitaxial silicon layer 106. This reduces the depth of the active region and also leads to a poorly defined emitter-base junction (i.e., where the N+ and P- type dopant concentrations are approximately equal). Both of these results have a negative impact on the operational characteristics of the device.
What is desired is a method of forming a double polysilicon NPN transistor using a self-aligned process which does not result in an etching of the silicon layer 106 underlying the base contact polysilicon layer 110. Such a method would allow the desirable over-etching of the polysilicon layer 110 without the presently associated disadvantages of such a step.